III-V bipolar transistors are three terminal devices having three regions of alternating conductivity type, referred to as the emitter, base, and collector, constructed from III and V semiconductor compounds. One class of III-V bipolar transistors gaining notoriety is heterostructure devices—heterojunction bipolar transistors (“HBTs”) and double heterojunction bipolar transistors (“DHBTs”). HBT and DHBTs include a junction between materials of differing composition, such as InGaAs and InP. In such an exemplary device structure, the InGaAs material has several known distinct properties from the InP material. These characteristics are detailed in depth in various references, including Sze, Physics of Semiconductor Device, Wiley-Interscience, 1969, pp. 17-24 and 140-146 (hereinafter “Sze”), Williams, Gallium Arsenide Processing Techniques, Artech House, Inc., 1984, pp. 17-35 and 79-82 (hereinafter “Williams”), and Streetman, Solid State Electronic Devices, Prentice-Hall, Inc., 1980, pp. 52-96, 395-399, and 424-428 (hereinafter “Streetman”) which are hereby incorporated by reference.
Various methods of fabricating III-V DHBT devices are known in the art. Referring to FIG. 1, a multi-layer structure 5 is shown prior to undergoing the process steps for making a Ill-V DHBT device, as detailed in U.S. Pat. No. 5,907,165, commonly assigned with the present invention and hereby incorporated by reference. Structure 5 is grown using standard growth techniques as known in the art, such as Metal-Organic Molecular Beam Epitaxy (MO-MBE). Structure 5 comprises an InP substrate layer 10 on which a series of semiconductor layers 20 through 80 are sequentially grown. A subcollector layer 20 is formed overlying InP substrate layer 10 and comprises n+ doped InGaAs. Subcollector layer 20 also includes buffer layers to prevent unacceptable diffusion of impurities within the multilayer structure. The buffer layers comprise an n-doped InGaAs layer and an undoped InGaAs layer. An n− doped InP collector layer 30 is formed overlying subcollector layer 20.
III-V DHBTs are typically formed with buried junctions covered by thin graded quaternary layers to improve device reliability. Structure 5 of FIG. 1 comprises a base-collector and a base-emitter graded quaternary InGaAsP layer, 40 and 60, respectively. Collector-base graded quaternary layer 40 separates collector layer 30 from a base layer 50. Base layer 50 comprises a doped InGaAs. Collector-base graded quaternary layer 40 comprises a series of InGaAsP sublayers, including several buffer layers. These buffer layers are intended to improve transport characteristics and reduce current blocking, and comprise at least an n-doped InGaAs layer and an undoped InGaAs layer. Similarly, the emitter-base quaternary graded layer 60 comprises a series of InGaAsP sublayers for separating n-doped InP emitter layer 70 from base layer 50. Overlying emitter layer 70 is an n-type doped InGaAs emitter contact layer 80.
Referring to FIG. 2, a first series of steps are executed on the structure 5 of the known process is shown. Here, an emitter contact pad 90 is selectively formed overlying emitter contact layer 80 by a lift-off process, as is known in the art. A general description of the lift-off technique and its use may be found in U.S. Pat. Nos. 4,214,966, 5,620,909, 5,625,206, 5,656,515, and 5,903,037 each commonly assigned with the present invention, as well as Williams, pp. 125-127, all of which are incorporated herein by reference. Emitter contact 90 has a lateral dimension of approximately 3×5 μm.
As illustrated, emitter contact layer 80 is also wet or plasma etched using emitter contact pad 90 as an etch mask. An over-etch is performed to obtain an undercut as depicted under emitter contact pad 90 of 0.1 μm or more. Patterned contact layer 80 then serves as the etch mask for emitter layer 70 in a subsequent wet etch step. Subsequently, a base contact 100 is formed by evaporating a base contact metal using emitter contact pad 90 as a shadow mask to define the inner edge of base contact 100.
Subsequently, a base mesa is defined by a photolithographic resist step. The base mesa is thereafter selectively dry etched using BCl3/N2, thereby removing more than half the thickness of collector layer 30. The residual of collector layer 30 is then selectively wet etched and over-etched to produce an undercut. This undercut serves to reduce the base-collector capacitance of the III-V device. Thereafter, a collector contact 120 is deposited overlying the subcollector layer 20.
Referring to FIG. 3, a final series of steps are executed on the structure of FIG. 2 to create the known DHBT. First, the structure of FIG. 2 is passivated and encapsulated with a common layer 130, such as a polymer encapsulant. The device structure is then selectively dry etched to form via holes 140 through encapsulant layer 130. In so doing, access is gained to the collector, base and emitter metallization contacts, respectively, such that conductive plugs 150 are evaporated thereafter into via holes 140 to complete the device.
In the constant attempt to fabricate smaller III-V devices, it appears that the known art is limited to certain applications where the ability to finely dry etch via holes is not critical. Dry etching vias has proven effective for fabricating DHBTs having an emitter dimensions in the range of at least 2×4 μm to 3×5 μm. However, while the above known process for fabricating a III-V DHBT may provide, for smaller device construction, dry etching vias for a transistor having an emitter of less than 2×4 μm has proven difficult. At these dimensions, the dry etched vias are difficult to define using lithography. This is particularly relevant with respect to the base and emitter vias because of the intended smaller device size. Presently, in view of the drive for smaller devices, a commercial interest exists for a DHBT device with an emitter contact dimension of at least 1.2×3 μm, as well as a base and emitter contact spacing of less than 1 μm.
As a result, a method of manufacturing a DHBT is needed that will enable smaller device dimensions. Similarly, there is a demand for a process of fabricating a DHBT that is independent of dry etching vias to gain access to the base, emitter and collector contacts.